The present invention relates generally to packaging of power semiconductor devices, and more particularly to a method of assembling quad flat no-lead (QFN) power semiconductor packages.
High voltage and power semiconductor devices such as switching circuits and power MOSFET devices are with a variety of electronic devices. Typically, such circuits must be able to handle high currents and high power dissipation.
One way of packaging a power semiconductor die is to mount the die on a thick lead frame, electrically connect the die to the leads of the lead frame with a heavy gauge wire, and encapsulate the die and lead frame assembly with a molding compound. Thus, the thick lead frame must be able to accommodate the heavy gauge wire. Some such packages use soldered copper clips, but a special bonding tool is required to handle the clips.
Heavy gauge wires, copper clips and thick lead frames also are relatively expensive, increasing the overall packaging costs. Accordingly, it would be advantageous to be able to package power devices with less expensive materials yet provide improved thermal performance.